1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to an arrangement for reducing an access time. More specifically, the present invention relates to an arrangement for driving an internal data line pair at a high speed.
2. Description of the Background Art
In a semiconductor memory device, an increase in storage capacity leads to an increase in the number of memory cells. Accordingly, bit lines and internal data lines become longer. As the bit lines and the internal data lines for transmitting data get longer, associated parasitic capacitance increases. In order to reduce such parasitic capacitance to transfer data at a high speed, a hierarchical I/O line arrangement is utilized in which signal lines for transmitting data are divided.
FIG. 23 is a schematic representation of an arrangement of an array portion of a conventional semiconductor memory device. In FIG. 23, a memory array MA is divided into a plurality of memory blocks MB00-MBmn. Memory blocks MBi0-MBin (i=0-m) arranged in alignment in a row-direction form a row block and share a word line. Memory blocks MB0j-MBmj (j=0-n) arranged in alignment in a column-direction share a column select line extending from a column decoder. Each of memory blocks MB00-MBmn has memory cells arranged in a matrix of rows and columns.
For each of memory blocks MB00-MBmn, a local data line pair LIO is disposed. In one example, in a column block including memory blocks MB00-MBm0, local data line pairs LIOa and LIOb are arranged on either side in the column-direction of a memory block MBiO. The local data line pair disposed between adjacent memory blocks MBiO and MB (i+1)0 in the column-direction is shared by these adjacent memory blocks.
In the column block including memory blocks MB0n-MBmn, local data line pairs LIOc and LIOd are disposed corresponding to each memory block. Similarly in this column block, local data line pairs LIOc and LIOd are shared by adjacent memory blocks in the column-direction.
A global data line pair GIO extending in the column-direction is provided in common to the memory blocks in a column block. Global data line pair GIO is coupled through a block select gate BSG to a local data line pair contained in a corresponding column block. In FIG. 23, local data line pair LIOa is coupled to a global data line pair GIOa via a block select gate BSGa, and local data line pair LIOb is coupled to a global data line pair GIOb via a block select gate BSGb. In addition, local data line pair LIOc is coupled to a global data line pair GIOc via a block select gate BSGc, and local data line pair LIOd is coupled to a global data line pair GIOd via a block select gate BSGd. These block select gates BSGa-BSGd are rendered conductive according to a row block select signal. Thus, in one column block, one memory block is selected, and the corresponding local data line pair is coupled to the corresponding global data line pair GIO through a block select gate.
Global data line pairs GIOa-GIOd are coupled in common to a write/read circuit WRC. Write/read circuit WRC includes a write driver for transmitting write data and a main amplifier for amplifying memory cell data. Write/read circuit WRC is coupled via a main data line pair MIO to an input/output buffer circuit, not shown. In the write/read circuit WRC, a write circuit or a read circuit corresponding to a selected column block is activated according to a column block select signal.
FIG. 24 is a diagram representing the arrangement of a portion related to a memory block in a memory array shown in FIG. 23. In a memory block MB, memory cells MC are disposed in a matrix of rows and columns. For each column of memory cells, a bit line pair BLP is disposed, and for each row of memory cells, a word line WL is disposed. The word line WL is provided in common to the memory blocks included in a row block. FIG. 24 shows representatively a word line WL, a bit line pair BLP, and a memory cell MC disposed corresponding to an intersection of bit line pair BLP and word line WL. Bit line pair BLP includes bit lines BL and ZBL for transmitting complementary data signals. Memory cell MC is disposed corresponding to an intersection of bit line BL or ZBL and word line WL. In FIG. 24, memory cell MC is disposed at an intersecting portion of bit line BL and word line WL.
Bit line pair BLP is coupled to a sense amplifier SA via a bit line isolating gate BIG. Sense amplifier SA is shared by memory block MB and another memory block not shown. Bit line isolating gate BIG is made to conduct in response to a bit line isolating instruction signal .phi.BLI. When the other memory block sharing the same sense amplifier SA is selected, bit line isolating instruction signal .phi.BLI attains a low or logic "L" level, causing memory block MB to be isolated from sense amplifier SA.
Sense amplifier SA is coupled to a local data line pair LIO through a column select gate CSG rendered conductive in response to a column select signal Y on a column select line CSL. Local data line pair LIO includes local data lines LI/O and ZLI/O provided corresponding to bit lines BL and ZBL, for transmitting complementary data signals.
Local data line pair LIO is connected to global data line pair GIO via a block select gate BSG rendered conductive in response to a row block select signal .phi.RB. Global data line pair GIO also includes complementary data lines GI/O and ZGI/O and is coupled to a main amplifier MAP.
Each of bit line isolating gate BIG, column select gate CSG, and block select gate BSG is formed by a transfer gate consisting of an MOS transistor. Now, the operation will be briefly described.
First of all, when word line WL is selected according to an address signal, the voltage of word line WL is raised and the information stored in memory cell MC is transmitted to bit line BL. Bit line isolating instruction signal .phi.BLI is at a high or logic "H" level, and bit lines BL and ZBL are coupled to sense amplifier SA. A paired memory block, not shown, is isolated from sense amplifier SA. When data is read from memory cell MC, sense amplifier SA, in turn, is activated and differentially amplifies the voltages of bit lines BL and ZBL. Since the data from the memory cell is not read out on bit line ZBL, the voltage on bit line BL is amplified, with the voltage on bit line ZBL used as the reference voltage. After differentially amplifying the voltage of bit lines BL and ZBL, sense amplifier SA holds the amplified voltages.
Thereafter, the column select operation begins. Column select signal Y transmitted from the column decoder (not shown) on column select line CSL attains the logic "H" level of the selected state, and column select gate CSG is made to conduct, thus allowing the data held by sense amplifier SA to be transmitted on local data line pair LIO. Block select gate BSG is rendered conductive according to row block select signal ORB while the word line is selected, and connects local data line pair LIO to global data line pair GIO. Therefore, when column select gate CSG is made to conduct and data is transmitted on local data line pair LIO, the data on local data line pair LIO is transmitted to global data line pair GIO via block select gate BSG. The data on global data line pair GIO is amplified by main amplifier MAP and is transmitted to an output buffer circuit, not shown.
Local data line pair LIO is provided only for memory block MB. The number of column select gates CSG connected to local data line pair LIO is relatively small so that the parasitic capacitance of local data line pair LIO is also relatively small. Moreover, global data line pair GIO is provided in common to the memory blocks in the column block and only block select gates BSG are connected to global data line pair GIO so that the parasitic capacitance of global data line pair GIO is also relatively small. Thus, since the parasitic capacitance of local data line pair LIO and global data line pair GIO is relatively small, data may be transmitted to main amplifier MAP by driving local data line pair LIO and global data line pair GIO by sense amplifier SA. Main amplifier MAP drives main data line pair MIO shown in FIG. 23. Parasitic capacitance of main data line pair MIO is a line capacitances which is relatively small. Further, main amplifier MAP is provide only for global data line pair, and main amplifier MAP can be made relatively large in size so that it can transmit data to the output buffer circuit at a high speed. Thus, even when the storage capacity is larger, data can be read out at a high speed.
Even with the hierarchical I/O arrangement consisting of local data lines and global data lines shown in FIGS. 23 and 24, however, when the storage capacity increases, the length of global data line pair GIO increases accordingly, leading to non-negligible line capacitance. As a result, signal propagation delay occurs, and the high-speed access becomes difficult. In particular, when data is read, column select signal Y is transmitted along the column-direction, and the data from a selected memory block is transmitted, via global data line pair GIO, in the opposite direction along the column-direction. Thus, as storage capacity increases and the size or geometric feature in the column-direction becomes larger, the time from the column selection operation to the amplification of data by main amplifier MAP gets this disadvantageously long. For instance, in the arrangement shown in FIG. 23, if memory block MB00 is selected, since the column decoder is normally disposed near write/read circuit WRC, column select signal Y is transmitted in a direction from memory block MBm0 to memory block MB00, for the column select operation. Thereafter, data from the selected column is read out, and the read data is transmitted via global data line pairs GIOa and GIOb, in the direction opposite to the direction in which the column select signal is propagated. Since access time is determined by the worst case, the time required to read out the data from the memory block farthest away from the column decoder determines the access time. Therefore, if the signal propagation delay of the global data line becomes long, a high-speed data read operation becomes impossible.
Moreover, an increase in the number of memory blocks included in a column block leads to an increase in the number of block select gates BSG, which results in increased parasitic capacitance of the global data line pair and in increased line capacitance, causing the signal propagation delay. Furthermore, parasitic capacitance of local data line pair LIO caused by a column select gate connecting thereto becomes non-negligible for a high-speed read operation.
One arrangement intended for a data read operation at the highest possible speed to solve the above problems is described in Japanese Patent Laying-Open No. 5-54634.
FIG. 25 is a diagram representing another arrangement of the conventional hierarchical I/O line pair arrangement described in the abovementioned prior art document. FIG. 25 shows the arrangement of a portion related to one bit line pair BLP. Bit line pair BLP is provided with an equalizing circuit EQ for equalizing the potential of bit line pair BLP to an intermediate potential during a standby cycle, a sense amplifier SA for differentially amplifying the voltages of bit line pair BLP, a write select gate WSG rendered conductive according to column select signal Y for connecting bit line pair BLP and write data transmission line pair WI in a data write operation, and a read select gate RSG for transmitting the voltages on bit line pair BLP to local data line pair LIO according to column select signal Y in a data read operation. In the arrangement shown in FIG. 25, write data and read data are transmitted through separate signal line pairs.
Write select gate WSG includes n-channel MOS transistors T5 and T6 rendered conductive in response to the activation of write operation activating signal WE in a data write operation, and n-channel MOS transistors T7 and T8 rendered conductive upon the activation of column select signal Y for connecting bit line pair BLP with write data line pair WI via transfer gates T5 and T6.
Read select gate RSG includes n-channel MOS transistors T1 and T2 for receiving at their gates the voltages on bit lines BL and ZBL of bit line pair BLP and n-channel MOS transistors T3 and T4 rendered conductive in response to the activation of column select signal Y for connecting MOS transistors T1 and T2 to local data line pair LIO. The sources of MOS transistors T1 and T2 are connected to a ground node.
Additionally, a load circuit LOAD and a block select gate BSG are connected to local data line pair LIO. Load circuit LOAD includes p-channel MOS transistors T9 and T10 forming a current mirror circuit for supplying current to local data line pair LIO and a p-channel MOS transistor T11 rendered conductive when block select signal .phi.BR is deactivated for equalizing the voltages of respective data lines of local data line pair LIO.
Block select gate BSG includes transfer gates T12 and T13 formed by n-channel MOS transistors receiving at their gates the voltages on the data lines of local data line pair LIO, and n-channel MOS transistors T14 and T15 for connecting transfer gates T12 and T13 to global data line pair GIO according to block select signal .phi.BR. MOS transistors T12 and T13 each has one conduction node connected to a ground node. Global data line pair GIO is coupled to main amplifier MAP.
In the arrangement shown in FIG. 25, write operation activating signal WE is activated in a data write operation, and MOS transistors T5 and T6 in write select gate WSG are rendered conductive. When column select signal Y is activated or in a logic "H" level, MOS transistors T7 and T8 of write select gate WSG are made conductive and write data line pair WI is connected to bit line pair BLP. Data transmitted to write data line pair WI is transmitted to bit line pair BLP, and the data is written into a selected memory cell connected to bit line pair BLP.
On the other hand, in a data read operation, write operation activating signal WE is in the deactivated state or at a logic "L" level and write select gate WSG maintains its non-conductive state. Block select signal .phi.BR for the selected memory block attains a logic "H" level, and MOS transistor T11 in load circuit LOAD becomes non-conductive. Voltage equalization of local data line pair LIO is stopped and MOS transistors T9 and T10 operate as a current supply circuit. When the memory cell data is read out and the voltage difference is developed on bit line pair BLP, column select signal Y is driven to a logic "H" level or the selected state. In read select gate RSG, MOS transistors T3 and T4 are rendered conductive, and MOS transistors T1 and T2 are connected to local data line pair LIO. The gates of these MOS transistors T1 and T2 are connected to bit lines BL and ZBL, respectively. Thus, depending on the voltage difference between the bit lines BL and ZBL, the conductances of MOS transistors T1 and T2 differ and the magnitudes of discharge currents from the data lines of local data line pair differ, causing the voltage difference on local data line pair LIO. The voltage difference of local data line pair LIO is transmitted to the gates of MOS transistors T12 and T13 included in block select gate BSG. MOS transistor T14 and T15 are made conductive by state of block select signal .phi.BR in the selected state. Therefore, data lines of global data line pair GIO are driven by MOS transistors T12 and T13, creating between the data lines of global data line pair GIO the voltage difference sensed and amplified by main amplifier MAP.
In read select gate RSG in the arrangement shown in FIG. 25, the gates of MOS transistors T1 and T2 receive the voltages of bit lines BL and ZBL. Thus, column select signal Y can be driven to the selected state before the activation of sense amplifier SA so that data can be read out at a fast timing. In addition, since current amplification is performed on global data lines and local data lines, data can be read at a higher speed than in the case of voltage amplification.
As shown in FIG. 25, in the case of the arrangement in which the voltage difference of the bit line pair is converted into a current difference before it is read out, there is a need to provide a read gate RSG for each bit line pair and a current mirror-type load circuit for each local data line pair LIO. As a result, the area occupied by the column select portion, and thus the chip area, becomes larger when compared with the typical arrangement of the column select gate formed by a pair of switching transistors. In addition, there is a need to provide a current mirror-type load circuit and a block select gate for each local data line pair, which results in an increased area occupied by the circuitry provided in the connecting portions between the local data line pairs and global data line pairs.
FIG. 26 is a diagram representing the arrangement of a load circuit LIO shown in FIG. 24. In FIG. 26, load circuit LD includes an equalizing transistor T22 rendered conductive during the activation (logic "L" level) of an equalizing instruction signal .phi.EQZ for equalizing the voltages of data lines GI/O and ZGI/O of global data line pair GIO, and p-channel MOS transistors T20 and T21 rendered conductive during the deactivation of a write driver activating signal .phi.WDE for pulling up global data lines GI/O and ZGI/O to the power-supply voltage Vcc level. Global data line pair GIO is provided with a write buffer driver WBD activated in response to the activation of write driver activating signal .phi.WDE for generating write data from the data on main data line pair MIO and transmitting the write data to global data line pair GIO, and a main amplifier MAP activated in response to a main amplifier activating signal .phi.MPE for amplifying the data on global data line pair GIO.
A plurality of block select gates BSG are connected to global data line pair GIO. The operation of load circuit LD will be described briefly with reference to the signal waveform diagram shown in FIG. 27.
An equalizing instruction signal .phi.ZEQ stays at a logic "H" level for a prescribed period according to an address transition detecting signal. When equalizing instruction signal .phi.ZEQ attains the logic "H" level, the data from the selected memory cell is read out on global data line pair GIO according to a column select signal. In a data read operation, MOS transistors T20 and T21 in load circuit LD are in the conductive state. Thus, the voltage levels of global data line pair GIOs change to those determined by the ratio of the resistances of MOS transistors of the sense amplifier to the on resistances of MOS transistors T20 and T21 of load circuit LD, and small amplitude voltage signals are transmitted. When the voltage difference on global data line pair GIO becomes sufficiently large, main amplifier activating signal .phi.MPE is activated, causing main amplifier MAP to amplify the signals on global data line pair GIO and transmits the amplified signal on main data line pair MIO.
After a prescribed period of main amplifier activating signal .phi.MPE being in the activated state or at a logic "H" level, when the reading of the data on global data line pair is completed, main amplifier activating signal .phi.MPE becomes deactivated or attains a logic "L" level, and main amplifier MAP is deactivated. Then, equalizing instruction signal .phi.ZEQ is activated or attains a logic "L" level, thereby making equalizing transistor T22 conductive, which starts the equalization of the voltages of global data line pair GIO. In a data read operation, the voltage amplitude of global data line pair GIO is small, so that global data line pair GIO is precharged to the power-supply voltage Vcc level in a relatively short time.
Similarly, in a data write operation, equalizing instruction signal ZEQ is driven to the deactivated state or the logic "H" level according to the transition of address. In accordance with the column select operation, global data line pair GIO is connected to the selected column, and the voltage level of global data line pair GIO change depending on the latch data of the sense amplifier. Thereafter, write driver activating signal .phi.WDE is set to a logic "H" level for a prescribed period, causing write buffer driver WBD to operate to generate internal write data according to the data signals provided through main data line pair MIO. During the operation of write buffer driver WBD, MOS transistors T20 and T21 in load circuit LD are in the non-conductive state. Therefore, global data line pair GIO is driven to the power-supply voltage Vcc level and the ground voltage level according to the internal write data. The voltages Vcc and GND on global data line pair GIO are transmitted on the selected column for writing of the data.
When the write operation is completed, write driver activating signal WDE is deactivated or attains a logic "L" level, and thereafter, equalizing instruction signal .phi.ZEQ at the logic "H" level is activated and attains the logic "L" level. When write driver activating signal .phi.WDE attains a logic "L" level, MOS transistors T20 and T21 in load circuit LD are made conductive to effect the pull up of the data line at the ground voltage level, of global data line pair GIO. Then, equalizing instruction signal .phi.ZEQ is activated, whereby equalizing transistor T22 is rendered conductive to equalize the voltages of global data line pair. Finally, the voltages of global data line pair GIO recover to the power-supply voltage Vcc level. The use of load circuit LD allows the transmission of a small amplitude signal in the read operation, and a successful high-speed data read operation is realized.
In the data write operation, however, load circuit LD is deactivated, and data lines GI/O and ZGI/O of global data line pair GIO are driven to the power supply voltage Vcc and ground voltage GND levels. Global data lines GI/O and ZGI/O are charged by MOS transistors T20 and T21 after the completion of the write operation. If the load (parasitic capacitance) of global data lines GI/O and ZGI/O is large, global data lines GI/O and ZGI/O cannot recover to the power-supply voltage Vcc level at a high speed.
Supposing that, after the completion of the data write operation, the data read operation is performed before global data line pair GIO fully recovers to the original voltage level as shown by (A) in FIG. 28, time ta will be required before the voltages of global data line pair GIO are made definite according to the read data. Particularly, a longer time is required when reading data is the inverse of the written data.
On the other hand, when the data read operation is performed after global data line pair GIO recovers to the power supply voltage Vcc as shown by (B) in FIG. 28, the voltage changes from the power supply voltage Vcc according to the read data, and the time required for the voltages of global data line pair GIO to be definite is time tb. Thus, if the write recovery time, or the time required for global data line pair GIO to recover to the original voltage level, is long, the read operation cannot follow the write operation in a short time, which makes high-speed access impossible. Particularly, when write and read operations are performed alternately by using a page mode or the like, a high-speed page operation becomes impossible. In addition, with a clock synchronous semiconductor memory device in which writing and reading of data are performed in synchronization with a clock signal, when data is read after the completion of the write operation and if global data line pair is not allowed to recover fully to the original voltage level within the short clock cycle, data cannot be written or read in synchronization with a high-speed clock (because an attempt to read soon may lead to the reading of incorrect data). Moreover, when data lines are equalized in each clock cycle, the clock cycle cannot be short, and thus, a high-speed write operation cannot be performed.